Integrated circuit chips often utilize special output driver circuit topologies for high speed communication of binary logic voltages to other integrated circuit chips in spite of appreciable interconnection capacitance.
FIG. 1 is a schematic/block diagram illustration of a typical output driver. An output driver 100 on a first integrated circuit chip 110 is connected at circuit node 120 to an input buffer 130 on a second integrated circuit chip 140. Output driver 100 comprises a pullup device, such as n-channel metal-oxide-semiconductor (NMOS) pullup field-effect transistor (FET) 150, and a pulldown device, such as NMOS pulldown FET 160. Pullup FET 150 has a drain terminal coupled to a first voltage, such as a positive power supply voltage, at node 170, a gate terminal receiving a first input signal at node 180, and a source terminal coupled to circuit node 120. Pulldown FET 160 has a source terminal coupled to a second voltage, such as a negative power supply or ground voltage, at node 190, a drain terminal coupled to circuit node 120, and a gate terminal receiving a second input signal at node 200.
In FIG. 1, circuit node 120 is switched from a binary low logic voltage (low) to a binary high logic voltage (high) by holding second input signal 200 low while transitioning first input signal 180 from low to an elevated binary high logic voltage (elevated high), which is more positive than the power supply voltage at node 170. Pullup FET 150 turns on, sourcing current to circuit node 120 to raise its voltage to approximately the power supply voltage at node 170. Circuit node 120 is returned low by transitioning the first input signal at node 180 from elevated high to low and transitioning the second input signal at node 200 from low to elevated high. Pullup FET 150 turns off, and pulldown FET 160 turns on, sinking current from circuit node 120 to lower its voltage to approximately the ground voltage at node 190.
The rate at which circuit node 120 can be switched between low and high is increased by using NMOS pullup and pulldown FETs 150 and 160 respectively, rather than p-channel metal-oxide-semiconductor (PMOS) FETs, which typically have a lower process transconductance. The switching rate of circuit node 120 is also increased by using the elevated high potential, which is more positive than the power supply voltage at node 170, to turn on pullup and pulldown FETs 150 and 160 respectively. The elevated high potential increases the current sourcing and sinking capability of pullup and pulldown FETs 150 and 160, respectively, and also ensures that the output voltage at node 120 is fully raised to approximately that of the power supply voltage at node 170 in a steady state.
FIG. 2 illustrates generally a switching of the voltage 301 at circuit node 120 by the output driver of FIG. 1. Voltage and time are respectively indicated by y-axis 300 and x-axis 310. Voltage level 320 corresponds to power supply node 170 and the voltage level 330 corresponds to ground node 190. Requirements of a minimum output high voltage, V.sub.OH 340, and maximum output low voltage, V.sub.OL 350, are determined by the input requirements of input buffer 130 and desired noise margins.
FIG. 2 illustrates certain limitations of the output driver of FIG. 1 for high speed switching of circuit node 120. First, a transition switching voltage 301 at circuit node 120 between the voltage level 330 at ground node 190 and the voltage level 320 at power supply node 170 typically exceeds the minimum voltage transition 360 required for proper interpretation of low and high binary logic voltages. This extra voltage excursion increases switching time and power consumption. Second, such a transition in voltage 301 of circuit node 120 is sometimes accompanied by ringing, which may require additional settling time before low and high binary logic voltages can be properly interpreted.